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Global descriptor tableComplex instruction set computerLoad-link/store-conditionalCpuidDynamic loadingControl/status registerCpu modesLoadable kernel moduleIa-32Execute instructionIoctlIllegal opcodeProgram counterAddress generation unitIndirect branchLong modeEmm386Dynamic linkerMachine code monitorSwarNo instruction set computingCache replacement policiesMachine codeInput/output base addressMicrosoft windows library filesPower3Segment descriptorMultiple instruction, single dataMemory address registerRuntime libraryMulti-core processorGeneral protection faultCache prefetchingInstruction registerNon-uniform memory accessIntel 5-level pagingDirect memory accessSpecial function registerMemory-level parallelismMemtest86Memory buffer registerModel-specific registerTask parallelismIa-64Microarchitectural data samplingSuperscalar processorPeek and pokeDos memory managementClmul instruction setAdvanced vector extensionsMemory-mapped i/oSystem callTrace cacheProcessorDll injectionInline assemblerPower4Advanced matrix extensionsCrt0Expanded memoryFma instruction setInstruction set simulatorBit testSymmetric multiprocessingMicro-operationProtected modeMicrocodeMicroarchitectureBank switchingAssembly languageSupervisor mode access preventionControl registerAgesaInstallable file systemBinfmt miscModified harvard architectureInterrupt descriptor tableAdvanced power managementIntel adxTransactional memoryHyper-threadingStreaming simd extensionsProgrammable interrupt controllerBiosIo uringIntel 80486 overdriveRegister allocationData in useMotorola 68000 seriesStack machineMemory pagingAtmel arm-based processorsCpu cacheJava classloaderLate bindingCache-oblivious algorithmRuntime systemPortable executableMemory addressBoot sector