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Tomasulo's algorithm Superscalar processor Swar Microarchitecture Instruction scheduling Simultaneous multithreading Address generation unit Special function register Task parallelism Register renaming Complex instruction set computer No instruction set computing Cpuid Non-uniform memory access Register allocation Gang scheduling Cache replacement policies Instruction register Multiple instruction, single data Multi-core processor Transactional memory Microcode Register-transfer level Symmetric multiprocessing Control/status register Trace cache Hyper-threading Branch target predictor Out-of-order execution Cpu cache Hardware-assisted virtualization Processor affinity Mesif protocol Frequency scaling Heterogeneous system architecture Automatic vectorization Program counter Programmable interrupt controller Processor Control register Model-specific register Dynamic frequency scaling Memory-level parallelism Amd accelerated processing unit Distributed shared memory Instruction set simulator Memory address register Structured concurrency Advanced host controller interface Microprocessor Cuda Kernel same-page merging Peterson's algorithm Cell Shared graphics memory Bus mastering Fair-share scheduling Supervisor mode access prevention Global descriptor table Network scheduler Treiber stack Fetch-and-add Compute kernel Reconfigurable computing Intel turbo boost Cache-oblivious algorithm Register machine Timer coalescing Cache coherence Dynamic loading Clmul instruction set Memory buffer register Direct memory access Central processing unit Dynamic programming language Memory management unit Chipset Multiprocessor system on a chip Distributed algorithm Futex Asynchronous method invocation Openrisc Ticket lock Arm cortex-a57 Priority ceiling protocol Multiprocessor system architecture Operand forwarding Async/await Quantum programming System power management interface Strategy pattern Opencl Adaptive voltage scaling High-level synthesis Cpu modes Parallel programming model Micro-operation Accumulator Intrinsic function Execute instruction

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